PRZOOM - /newswire/ -
San Jose, CA, United States, 2011/10/14 - This paper will give an overview and details regarding what aspects of the IP are checked and how the information is used to assess IP completeness, readiness and integration risks.
This paper will also review the process needed to install, setup and run the software and share some results of its application on production-level soft IP blocks.
Anuj Kumar, Sr. Manager of the Customer Consulting Group at Atrenta
Tuesday, October 18, 2011; 1:00 PM - 1:30 PM, Pacific Time
TSMC Open Innovation Platform Ecosystem Forum, San Jose Convention Center, San Jose, Calif., USA.
As much as 80% of an SoC (system on chip) may be comprised of soft IP blocks. It's crucial for SoC designers to know the quality, completeness and integration risks associated with the soft, or synthesizable semiconductor IP they use. This knowledge is critical to meeting power, performance, area and schedule targets for complex SoC designs.
Atrenta has collaborated with TSMC to create a comprehensive system to automate the process of soft IP qualification. Based on the Atrenta SpyGlass® platform, the system programmatically analyzes soft IP using an IP handoff methodology consisting of TSMC's Golden Rule Set covering various design parameters (e.g., risk analysis, integration readiness, implementation readiness, reusability) for a soft IP block.
• Atrenta is exhibiting at booth #213
• For information about the TSMC OIP Ecosystem forum, please visit lookingcube.com/.
Atrenta (atrenta.com), SpyGlass and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press advisory.
Liz Massingill, Lee PR
E: liz[.]leepr.com / T: +1-650-363-0142