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3D IC Packaging - Unavoidable Technology for Miniaturization and Increased Performance - The technical issues for innovative 3D packaging at the wafer level are close to be solved. The new market research report defines 3D as the most
3D IC Packaging - Unavoidable Technology for Miniaturization and Increased Performance

 

PRZOOM - /newswire/ - Montréal, Québec, Canada, 2007/11/27 - The technical issues for innovative 3D packaging at the wafer level are close to be solved. The new market research report defines 3D as the most "integrated" approach and as an enabling technology platform.

   
 
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Electronics.ca Publications, the electronics industry market research and knowledge network, announces the availability of a new report entitled "3D IC & TSV Report".

The technical issues for innovative 3D packaging at the wafer level are close to be solved. The new market research report defines 3D as the most "integrated" approach and as an enabling technology platform applicable to digital and mixed signal electronics, wireless, electro-optical, MEMS, sensors, smart imagers, displays and other devices.

Semiconductor chips face constant pressure for increased performance while still decreasing their size and at the same time their packages must be able to accommodate new functionalities. The ever-expanding consumer electronics market is a particularly strong driver of packaging innovations such as 3D ICs. Today wire bonding is limited in density and performances so 3D stacking with micro-vias (or TSV, "through-Si vias") seems to be unavoidable in the future for miniaturization first and increased performance after.

3D integration will use technologies originally developed for MEMS technology but for different markets. According to the report, portable applications are strong market drivers for 3D integration. Stacking memories, stacking memories and logic, image sensors with µP and FPGAs will be the first mass market applications. In 2010, it is forecasted that 1 billion of Flash memories will be stacked with TSVs.

"3D IC & TSV" is an ultimate report to weight the strength and weakness of existing 3D ICs technologies and see who is doing what in term of 3D packaging among the key players. It includes the status of developments, how it will impact the semiconductor food chain. It covers as well equipments market forecasts and technical analyses of the different solutions with extensive exclusive technical explanation, figures and abstracts.

Details of the new report can be found on Electronics.ca Publications' website.

 
 
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Agency / Source: Electronics.ca Publications

 
 

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3D IC Packaging - Unavoidable Technology for Miniaturization and Increased Performance

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Contact: Chiaki Sadanaga 
1-514-907-2112 pr[.]electronics.ca
 
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