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VeriEZ Announces SystemVerilog® Design and Verification Productivity Tool Suite - EZVerify to address productivity across Design, Assertions and Testbench language subsets
VeriEZ Announces SystemVerilog® Design and Verification Productivity Tool Suite

 

PRZOOM - /newswire/ - Santa Clara, CA, United States, 2007/05/07 - EZVerify to address productivity across Design, Assertions and Testbench language subsets.

   
 
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VeriEZ Solutions, Inc., the Verification Tools Company, today announced the immediate availability of EZVerify, a SystemVerilog Productivity tool suite for Design and Verification Engineers.

By creating the industry’s first productivity tool suite to address the complete SystemVerilog language, VeriEZ is providing SystemVerilog adopters with robust tools for designing and verifying complex designs.

“SystemVerilog is well on its way to becoming a defacto standard for design and verification of electronic systems,” said Sashi Obilisetty, VeriEZ’s president and CEO. “Its many advantages are best exploited by putting together a consistent methodology. EZVerify’s capabilities will enable engineers to successfully implement SystemVerilog-based projects.”

EZVerify utilizes static analysis techniques to provide an environment for creating reusable and error-free modules in SystemVerilog. It consists of two components: EZCheck (configurable static analyzer) and EZReport (verification knowledge extractor).

EZCheck Static Analyzer

EZCheck parses SystemVerilog files, and applies selected “rulesets” to user-supplied input. Rulesets are rule collections that inputs should comply with. Prepackaged rulesets are included for Design Analysis (for RTL Synthesis), Functional Coverage Model and Verification Analysis (for verification models), Assertions Analysis (for ABV) and Model Portability.

EZCheck also includes rulesets to improve productivity of Synopsys Verification Methodology Manual (VMM) based project implementations. Future versions will support other industry standard verification methodologies.

EZReport Knowledge Extractor

EZReport is designed to provide an instant reuse platform for product teams. EZReport creates comprehensive knowledge documents that enables engineers to understand existing components and make reuse decisions. Information regarding object hierarchy, assertion density, interfaces and concurrency mechanisms is provided in web-ready format.

EZReport includes required interfaces to generate documentation in the Doxygen format.

Pricing and Availability
EZVerify for SystemVerilog is available now. Annual licensing fees starts at $20,000 USD.

VeriEZ product demonstrations can be viewed in VeriEZ’s booth (#2857) at DAC (June 4-7, 2007, San Diego, California).

About VeriEZ
VeriEZ Solutions, Inc. (veriez.com) is a privately held EDA company that develops and markets solutions that enable efficient chip verification. It is the developer of EZVerify and EZTranslate Tool Suites. EZVerify is the industry’s first Design and Verification Productivity Tool Suite for SystemVerilog® and OpenVera™. It includes a configurable static analyzer (EZCheck) and a verification knowledge extractor (EZReport). EZTranslate is an OpenVera-to-SystemVerilog Migration Tool Suite. VeriEZ’s tools detect errors and enable reuse.

All trademarks or registered trademarks are the property of their respective holders.

 
 
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VeriEZ Announces SystemVerilog® Design and Verification Productivity Tool Suite

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Contact: Sashi Obilisetty - VeriEZ.com 
408-988-1604 x1 sashi[.]veriez.com
 
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