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Atrenta and Mentor Collaborate on SoC Power Signoff - Atrenta, Inc. announced that it is collaborating with Mentor Graphics Corp. to enable accurate, signoff quality power estimation at the register transfer level (RTL) for the entire system on chip (SoC) device (NASDAQ: MENT) - Mentor.com / Atrenta.com
Atrenta and Mentor Collaborate on SoC Power Signoff

 

PRZOOM - /newswire/ - San Jose, CA, United States, 2013/05/30 - Atrenta, Inc. announced that it is collaborating with Mentor Graphics Corp. to enable accurate, signoff quality power estimation at the register transfer level (RTL) for the entire system on chip (SoC) device (NASDAQ: MENT) - Mentor.com / Atrenta.com.

   
 
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Atrenta, Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that it is collaborating with Mentor Graphics Corporation to enable accurate, signoff quality power estimation at the register transfer level (RTL) for the entire system on chip (SoC) device. The project aims to radically improve SoC design efficiency by facilitating RTL power estimation for designs in excess of 50 million gates, running actual software scenarios over hundreds of millions cycles, resulting in large simulation data sets in excess of 10Gbytes.

The collaboration between the two companies has resulted in an interface between the Mentor Veloce2 emulator and Atrenta's SpyGlass Power RTL power estimation tool to allow estimation of SoC power and validation of power budgets at the full-chip level. The interface files from the emulator significantly differ from files generated by standard RTL simulation tools since they are optimized for large data sets over millions of cycles. The collaboration enables SpyGlass Power to consume specific data generated by Veloce2 in switching activity interface format (SAIF) and files system database (FSDB) industry formats.

Traditionally, RTL power estimation is performed at the block level due to the lack of full-chip SoC simulation data for accurate dynamic power estimation in the different functional modes of the chip. SoC power is then calculated by adding the power numbers of the sub-blocks. The sum of the power of the blocks does not always correlate to the total power consumed by the chip due to the activity caused by complex interfaces between the sub-blocks. This often results in surprises during the final tapeout as the power budgets for the SoC can be way off.

"This collaboration will enable our customers to get signoff quality power estimates at RTL for the full SoC thanks to activity profiles generated by Mentor's Veloce2 emulator while running actual embedded and application software," said Piyush Sancheti, vice president of product marketing at Atrenta. "RTL power estimation with realistic application scenarios is a winning combination for low power design and optimization."

"Mentor is dedicated to providing the best possible low-power design and verification tools to drive our customer's success," said Eric Selosse, vice president and general manager, Mentor Emulation Division. "The cooperation with Atrenta is significant for Mentor and our customers to make sure that power issues get resolved early in the design cycle."

Atrenta and Mentor Graphics will showcase the results of this collaboration in their respective booths at the 50th Design Automation Conference (DAC) in Austin, Texas. For details and signup, please visit atrenta.com and mentor.com. The Veloce2/SpyGlass Power flow is available now. The respective tools can be purchased from Mentor Graphics and Atrenta.

About Atrenta
Atrenta's SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence.

About Mentor Graphics
Mentor Graphics Corporation (mentor.com) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of about $1,015 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

© 2013 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo and SpyGlass are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

Contacts:
Carole Dunn, Mentor
T: +1-503-685-5716 - E: carole_dunn[.]mentor.com.

Atrenta PR Agency: Lee PR, Liz Massingill
T: +1-650-363-0142 - E: liz[.]leepr.com.

 
 
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Atrenta and Mentor Collaborate on SoC Power Signoff

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IMPORTANT INFORMATION: Issuance, publication or distribution of this press release in certain jurisdictions could be subject to restrictions. The recipient of this press release is responsible for using this press release and the information herein in accordance with the applicable rules and regulations in the particular jurisdiction. This press release does not constitute an offer or an offering to acquire or subscribe for any SpyGlass® / Atrenta, Inc. securities in any jurisdiction including any other companies listed or named in this release.

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